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. features ? dc/dc step-up converter (boost) 3.3v to 5.2v, 1a, up to 90% efficiency. can be used as buck/boost in sepic configuration dc/dc step-down (buck) synchronous conver ter 0.9v to 3.4v, 500ma, up to 90% efficiency, pulse skipping capabilities for high efficiency at light load currents two low-drop-out regulators 1.3v, 1.5v to 1.8v, 2.5v to 2.8v (100 mv step), 3.3v, 200 ma maximum load ultra-low power real-time clock (rtc) and backup battery management ? 2.6v rtc ldo for backup battery charging ? 32 khz crystal rtc oscillator (1 a) ? rtc circuit for time and date information activation of the power management modules via dedicated enable pin automatic start-up se quences, pok signal indicating when start-up is completed activation and control of th e power management modules in dynamic mode (via spi or twi) or in static mode (on/off of the four power supplies) itb signal indicating short-circuits in dc/dc converters very low quiescent current minimum external components count supply: from 2.8v to 5.25v (typ: li-ion battery 3v to 4.2v) available in a 32-pin 5x5 qfn package applications include: ? wlan portable devices ? multimedia devices ? portable music players 1. description the AT73C224-X is a family of ultra low cost power management unit, available in a small outline qfn 5x5mm package. the AT73C224-X family is optimized for port able applications, typically powered by a li-ion battery. the AT73C224-X device is also suitable to operate from a standard 3.3v to 5.25v voltage rail. it includes four power supplies and a very low power real- time clock (rtc). in normal mode (main battery present), the backup battery is recharged through a 2.6v rtc ldo. the AT73C224-X series offer different aut omatic start-up sequences (with varying orders of power-on and specific default output values) and different soft management modes: dynamic (via spi or twi) with register access or static, with access to power on/off of the four power supplies. each AT73C224-X device is equipped with a very low power bandgap reference, low power 32 khz and 1 mhz oscillators and an internal ldo used to generate t he internal supply (vint) equal to 2.8v. auxiliary ce lls, such as a powe r-on reset (por) and a voltage monitor are used to control the system power-on (battery plugged in) and power-off (battery unplugged). the four power supplies are named: boost1, buck2, ldo3 and ldo4. table 1-1 lists the different devices available in the AT73C224-X series. power management and analog companions (pmaac) at73c224-a at73c224-b at73c224-c at73c224-d at73c224-e at73c224-f at73c224-g at73c224-h 4x channels power supply: dc/dc boost dc/dc buck 2x ldos rtc 6266a?pmaac?08-sep-08
2 6266a?pmaac?08-sep-08 at73c224 for more details concerning the automatic start-up sequences, see section 5.2 . for more details concerning the management modes, see section 5.3 . . table 1-1. AT73C224-X device series part number automatic start-up sequence order of power-on and output default values. management mode comments at73c224-a 1 - buck2= 1.8v 2 - ldo4 = 2.8v 3 - ldo3 = 2.7v dynamic boost1 can be activated after start-up sequence by a user command. at73c224-b 1 - buck2 = 1.2v 2 - ldo4 = 1.8v 3 - ldo3 = 1.8v dynamic boost1 can be activated after start-up sequence by a user command. at73c224-c 1 - ldo4 = 2.8v 2 - buck2 = 1.8v 3 - ldo3 = 2.7v dynamic boost1 can be activated after start-up sequence by a user command. at73c224-d 1 - ldo4 = 1.8v 2 - buck2 = 1.2v 3 - ldo3 = 1.8v dynamic boost1 can be activated after start-up sequence by a user command. at73c224-e 1 - boost11 = 5.2v 2 - ldo4 = 3.3v 3 - ldo3 = 3v dynamic buck2 can be activated after start-up sequence by a user command. ldo3 & ldo4 are supplied by boost1. (see section 4. ?application examples? , figure 4-3 on page 7 : application schematic 3.) at73c224-f 1 - buck2 = 1.8v 2 - ldo4 = 2.8v 3 - ldo3 = 2.7v static same as at73c224-a. at73c224-g 1 - ldo4 = 2.8v 2 - buck2= 1.8v 3- ldo3 = 2.7v static same as at73c224-c. at73c224-h 1 - boost1 = 5.2v 2 - ldo4 = 3.3v 3 - ldo3 = 3v static same as at73c224-e.
3 6266a?pmaac?08-sep-08 at73c224 2. block diagram figure 2-1. block diagram vdd3 vdd1 vsense1 dl1 vo1 vdd2 sw2 gnd2 vo2 gnd/avss vo3 gndana vdd4 vo4 vbat_ldortc vbackup xin xout vddio ck32 d1 d2 d3 d4 pok itb vbg vdd0 die paddle en vint vcapp vcapn 2 1 3 23 24 10 32 30 31 29 25 26 27 28 13 14 15 8 6 12 4 75 11 17 16 9 18 20 21 22 ldo3 vout 1.3v 1.5v-1.8v 2.5v-2.8v 3.3v iload 200 ma ldo4 vout 1.3v 1.5v-1.8v 2.5v-2.8v 3.3v iload 200 ma vbg por rtc rtc ldo rtc osc por, vmon (voltage monitor) lpvbg (low power vbg) vint regulator digital interface (twi / spi) pmc status register boost1 vout 3.3v-5.2v iload 1a buck2 vout 0.9v-3.4v iload 500 ma p n osc 900khz
4 6266a?pmaac?08-sep-08 at73c224 3. pinout table 3-1. at73c224 pinout pin name i/o pin # type function comments vo3 o 1 analog ldo3 output voltage ext. 2.2 f capacitor (mandatory) vdd3 ps 2 power ldo3 supply voltage gndana ps 3 ground analog ground vcapp i/o 4 analog not connected vint ps 5 power output of the internal ldo ext. 470 nf capacitor (mandatory) vdd0 ps 6 analog supply of the internal ldo must be connected to the main battery (mandatory) vcapn i/o 7 analog not connected vbg o 8 analog bandgap reference voltage should not be resistively loaded vdd2 ps 9 power buck2 supply voltage vbat_ldortc ps 10 power ldo_rtc supply voltage must be connected to the main battery (mandatory) vo2 i 11 analog buck2 output voltage en i 12 digital enable signal internal 100 k ? pull up d4 i 13 digital digital interface internal 100 k ? pull up pok o 14 digital power ok: indicates when start-up is completed itb/rdy i/o 15 digital user interrupt, gpio and shutdown control internal 100 k ? pull up sw2 o 16 analog buck2 inductor (nmos switcher output) gnd2 ps 17 ground buck2 ground vo1 i 18 analog boost1 output voltage dh1 o 19 analog not connected dl1 o 20 analog boost1 nmos control signal vsense1 i 21 analog boost1 current limitation sense voltage vdd1 ps 22 power boost1 supply voltage must be connected to the main battery vdd4 ps 23 power ldo4 supply voltage vo4 o 24 analog ldo4 output voltage ext. 2.2 f capacitor (mandatory) vddio ps 25 digital supply supply voltage for digital i/o d1 i 26 digital digital interface open drain d2 i/o 27 digital digital interface open drain d3 i 28 digital digital interface open drain ck32 o 29 digital 32 khz rtc output clock xout i/o 30 analog rtc crystal oscillator output xin i/o 31 analog rtc crystal oscillator input vbackup o 32 analog backup battery and rtc supply gnd/avss ps 33 ground main g nd and av ss ground die paddle connected to ground (mandatory)
5 6266a?pmaac?08-sep-08 at73c224 4. application examples figure 4-1. application schematic 1: microcontroller wit h 5v vbus for 2 usb host transceivers in the application schematic 1, the at7373c224-a is used: the boost(vo1) supplies the ?vbus? of two usb transceivers, the buck(vo2) supplies the digital core of the microcontroller, the ldo3 supplies the i/os of the microcontroller and ldo4 supplies analog cells, such as aux- iliary adc or pll. for external components, see table 4-1 . at73c224-a microcontroller vdd1 vsense1 dl1 dh1 vo1 vdd2 sw2 gnd2 vo2 gnd/avss vo3 gndana vdd4 vo4 vbat_ldortc vbackup xin xout vddio ck32 d1 d2 d3 d4 pok itb/rdy vbg vdd0 die paddle en vcapn vcapp vint v bat v bat vo1 vdd3 v bat pushbutton up up up nc nc nc itb/rdy up itb/rdy vddio (aux adc, pll) usb host transceiver usb host transceiver vcore spi / twi vo2 v bat v bat buck2 = 1.8v rst sck / twck sdo / twd d1 d2 d3 d4 sdi /adrress scs / gnd pok r2 c11 c8 c14 c3 c5 c10 c7 c13 c2 l2 q1 l1 d1 r1 c1 c6 c4 c9 c12 rechargeable backup battery (nbl type) v bat up up x1 boost1 = 5v (vbus usb) ldo4 = 2.8v ldo3 = 2.7v 3v to 4.2v v bat 1 32 c16 li-ion battery
6 6266a?pmaac?08-sep-08 at73c224 figure 4-2. application schematic 2: supply of a microprocessor and external analog cells in the application schematic 2, the at73c224- b is used: the boost (vo1) supplies the ?vbus? of one usb transceiver and supplies also ldo3 and ldo4. the buck(vo2) supplies the digital core of the microcontroller and the ld os supply the i/os and analog cells, such as auxiliary adc or pll. for external components, see table 4-1 . at73c224-b microcontroller analog cells vdd1 vsense1 dl1 dh1 vo1 vdd2 sw2 gnd2 vo2 gnd/avss vo3 gndana vdd4 vo4 vbat_ldortc vbackup xin xout vddio ck32 d1 d2 d3 d4 pok itb/rdy vbg vdd0 die paddle en vcapn vcapp vint v bat v bat vo1 vdd3 v bat button up up up nc nc itb/rdy up itb/rdy vddio vcore spi / twi vo2 nc v bat vo4 v bat v bat buck2 = 1.2v rst sck / twck sdo / twd d1 d2 d3 d4 sdi /adrress scs / gnd pok r2 c11 c8 c14 c3 c5 c10 c7 c13 c2 l2 l1 r1 c1 c6 c4 c9 c12 rechargeable backup battery (nbl type) v bat up up x1 q1 boost1 = 5v ldo4 = 1.8v d1 3v to 4.2v 1 32 c16 boost1 = 5v li_ion battery
7 6266a?pmaac?08-sep-08 at73c224 figure 4-3. application schematic 3: boost in sepic configuration (buck/boost) in the application schematic 3, the boost (vo1) is in sepic configuration (buck/boost) and generates a 3.3v output voltage for analog cells. the buck (vo2) supplies the core of the microcontroller, and ldo4 supplies the i/os. note that, in the sepic configur ation, the maximum lo ad current on vo1 should not exceed 300 ma. for external components, see table 4-1 . at73c224-b microcontroller analog cells vdd1 vsense1 dl1 dh1 vo1 vdd2 sw2 gnd2 vo2 gnd/avss vo3 gndana vdd4 vo4 vbat_ldortc vbackup xin xout vddio ck32 d1 d2 d3 d4 pok itb/rdy vbg vdd0 die paddle en vcapn vcapp vint v bat v bat vo1 vdd3 v bat button up up up nc nc itb/rdy up itb/rdy vddio vcore spi / twi vo2 nc v bat vo4 v bat v bat buck2 = 1.2v rst sck / twck sdo / twd d1 d2 d3 d4 sdi /adrress scs / gnd pok r2 c11 c8 c14 c3 c5 c10 c7 c13 c2 l2 l1 r1 c1 c6 c4 c9 c12 rechargeable backup battery (nbl type) v bat up up x1 c15 l3 q1 boost1 = 3.3v ldo4 = 1.8v d1 3v to 4.2v 1 32 c16 boost1 = 3.3v li_ion battery
8 6266a?pmaac?08-sep-08 at73c224 table 4-1. external components schematic reference reference manufacturer value c1 tantalum tps case b avx ? 100 f c2 tantalum tps case a avx 33 f c3, c4 grm155r60j225me15 c1005x5r0j225mt murata ? tdk 2.2 f c6 grm21br60j226me39 c2012x5r0j226mt murata tdk 22 f c5, c7, c8, c9, c11, c13 grm155r60j105ke19 c1005x5r0j105kt murata tdk 1 f c10 grm155r61a104ka01 c0603x5r0j104kt murata tdk 100 nf c12, c14 grm155r60j474ke18 c1005x5r1a474kt murata tdk 470 nf c15 grm188r60j475ke19 c1608x5r0j475kt murata tdk 4.7 f c16 grm188r60j106me47 c1608x5r0j106mt murata tdk 10 f l1 744773022 wurth ? elektronik 2.2 h l1, l3 (in sepic config.) 744773068 wurth elektronik 6.8 h l2 b82467-g0682-m epcos ? 6.8 h d1 mbrm120lt1 on semiconductor ? q1 si1470dh vishay ? x1 fx135b-327 fox 32.768 khz r1 (can be printed on the board (cu line)) lr2010r050j welwyn 50 m ? r2 mr-crg0402j2k2 tyco ? electronics 2 k ?
9 6266a?pmaac?08-sep-08 at73c224 5. detailed description the AT73C224-X is a family of power management units with four power supplies and an ultra low-power real-time clock. by choosing a specific ordering code ?x? from a to h, different automatic start-up sequences and management modes ca n be selected. the start-up sequence includes the order of power-on, as well as the default value of the power supplies (see section 5.2 ?automatic start-up sequences and shut-down? ). the user can after- wards change this default value via spi or twi, if the dynamic mode has been chosen (see section 5.3 ?digital control and protocol? ). 5.1 core the core of the AT73C224-X device integrates the following blocks: power-on-reset for the backup battery. internal switch and ldo dedicated to the backup battery. the output of the ldo_rtc is set to 2.6v and the switch is on when the main battery higher than 2.8v (charge of the backup battery).see section 7.7 for electrical details. real-time-clock digital bloc + 32 khz oscillator. power-on-reset for the main battery. voltage monitor (vmon) of the main battery. digital power management control (pmc) for automatic start-up sequences. digital output pok indicates when start-up is completed, whereas itb digital output signal informs the user (typically the microcontroller) of a default in t he dc/dcs (short-circuit) or too low main battery value. twi and spi protocol blocs. dc/dc step-up converter boost1: a 3.3v to 5.2v(100 mv step), 1a, asynchronous dc/dc step-up converter available for overa ll system requirements. the dc/dc can be implemented through proper ex ternal components in buck/boo st (sepic) configuration. the output voltage can be programmed via the internal registers. boost1 is supplied directly by the battery. dc/dc step-down converter buck2: a 0.9v to 3.4v, 500 ma fully integrated synchronous pwm dc/dc step-down converter. the output voltage can be programmed via the internal registers. a pulse skipping mode is available in order to improve efficiency at very light load current values. in order to guarantee very low supply voltage functionality, the controller is supplied by the max voltages between the main battery and the output of boost1 (vo1). buck2 can be directly supplied by the battery or by the output of boost1. ldo3: a 1.3v, 1.5v to 1.8v (100 mv of step), 2.5v to 2.8v (100 mv of step), 3.3v, 200 ma ? low drop out regulators. the output voltage can be programmed via the internal registers. ldo3 can work with supply from 1.8v up to 5.5v. this ldo can be supplied by the battery, by the output of boost1, or by the output of buck2. ldo4: same functionality than ldo3. main bandgap: 1.18v reference voltage. 900 khz oscillator. internal ldo (vint) at 2.8v for internal supply.
10 6266a?pmaac?08-sep-08 at73c224 5.2 automatic start- up sequences and shut-down 5.2.1 start-up/wakeup if the backup battery (only) is present, the rtc is running (1.2 a). this mode is called ?backup mode?. when the main battery is plugged in and voltage is higher than 2.8v, the ldo_rtc recharges the backup battery through an internal switch (if the main battery is lower than 2.8v, nothing happens, rtc still running). this mode is called ?standby mode?. note that when the battery is plugged in (and higher than 2.8v), a reset of the rtc is performed only if the backup battery was lower than 1.8v. now, the system waits for wake-up information coming from the pushbutton (en pin) or an rtc alarm. when one of the previous conditions occurs, the automatic start-up sequence starts (without any external commands). different automatic start-up sequences can be chosen from the AT73C224-X family (see figure 5-1 on page 11 and figure 5-2 on page 12 ). when the automatic start-up sequence has been completed, the pok signal (which is an open drain signal) goes high, thus implementing a sort of por for the user (i.e., a microcontroller) and enters into ?normal mode?. note: power on is controlled by default by an ex ternal pushbutton, connected on en pin (the en pad has an internal 100 k ? pull up). a switch can also be used as shown bellow but should be a request from the customer . 5.2.2 shut-down static and dynamic modes are explained in detail in section 5.3 . 5.2.2.1 static mode in static mode, the power-off condition is an or between the following conditions: main battery lower than 2.8v or electrical default in th e dc/dc (short-circuit). when power-off condition occurs, pok signal is cleared, then the AT73C224-X device waits for the signal itb/rdy to shut down all power supplies. 5.2.2.2 dynamic mode in dynamic mode, power-off condition is an or between the following conditions: electrical default in the dc/dc (short-circuit) or software shutdown. when main battery lower than 2.8v, an interrupt is generated on sign al itb/rdy. it is the responsib ility of the host microcontroller to perform a software shut-down by properly writing the AT73C224-X device registers through the serial interface. after that, the pok signal is cleared, and all is turned off. a check on the push- button is then performed to assure that it has been released, thus avoidi ng continuous on-off-on behavior. the ?normal? shutdown is performed by software. note that the microcontroller has to write the proper register to enable the power off (see section 6. ?register tables? ). en (default: pushbutton) en (on request: switch)
11 6266a?pmaac?08-sep-08 at73c224 figure 5-1 illustrates the complete automatic start-up sequence of the at73c224-a and at73c224-f, whereas figure 5-2 illustrates the automatic st art-up sequence of the other AT73C224-X device versions. figure 5-1. start up sequence of the at73c224-a and at73c224-f 3ms boost1 user command: . at73c224-a: through dynamic mode (using twi or spi) . at73c224-f: through static mode (using d1 pin) 45ms typ 3ms 3ms en (wake-up of the system) (pushbutton) vint (internal supply) pwrgdint (internal- vth = 1.6v) pok -> up (start-up sequence completed) vmon (internal vth = 2.8v) por (internal vth = 1.6v) vbat 36 ms typ. vbg 30 ms min automatic start-up sequence: buck2 (default value: 1.8v) ldo4 (default value: 2.8v) ldo3 (default value: 2.7v)
12 6266a?pmaac?08-sep-08 at73c224 figure 5-2. automatic start-up sequence of all other versions of the AT73C224-X device series boost1 user command: . at73c224-b: through dynamic mode (using twi or spi) boost1 user command: . at73c224-c: through dynamic mode (using twi or spi) . at73c224-g: through static mode (using d1 pin) boost1 user command: . at73c224-d: through dynamic mode (using twi or spi) buck2 user command: . at73c224-e: through dynamic mode (using twi or spi) . at73c224-h: through static mode (using d2 pin) 3ms 3ms at73c224-b, at73c224-g buck2 (default value: 1.2v) ldo4 (default value: 1.8v) ldo3 (default value: 1.8v) at73c224-c, at73c224-h buck2 (default value: 1.8v) ldo4 (default value: 2.8v) ldo3 (default value: 2.7v) at73c224-d, at73c224-i buck2 (default value: 1.2v) ldo4 (default value: 1.8v) ldo3 (default value: 1.8v) at73c224-e, at73c224-j boost1 (default value: 5.2v) ldo4 (default value: 3.3v) ldo3 (default value: 3v) pok (automatic start-up sequence completed) 3ms v
13 6266a?pmaac?08-sep-08 at73c224 5.3 digital control and protocol the AT73C224-X family offers a choice of de vices in static mode or dynamic mode (see table 1- 1 on page 2 ). in dynamic mode, the user can manage the chip via spi or twi. the selection between spi or twi is done at start-up via the d4 pin (see section 5.3.2 on page 14 ). 5.3.1 static mode when the AT73C224-X is established in static m ode, the digital interface signals, d1 to d4, directly drive the enable of the four supplies. during start-up, these enable signals are driven by the internal state machine. to ensure a safe transition between the start-up state and the estab- lished state, a handshake protocol must be res pected. this transition period is especially important in a microcontroller environment, as t he microcontroller controlling the d1-d4 signals may require an unknown period of time to actually drive these pins. in static mode, the itb/rdy pin is configured as an input with controllable pull-up resistor. when the internal state machine completes the supply start-up, it latches the value of itb/rdy and then sets the pok signal to 1. this means that start-up is accomplished. the state machine then checks for changes on itb/rdy. if no changes are detected, the control of the four supply chan- nels remains with the state machine. if a change is detected the internal pullup is disconnected and the control is passed on to d1-d4, with the assignment shown in table 5-2 below. the illustrations in figure 5-3 , figure 5-5 and figure 5-5 represent possible static mode scenarios. figure 5-3. fully static mode since itb/rdy is 1 or open (weak internal pullup), the state of each supply channel is deter- mined by the internal state machine (automat ic start-up sequence and default values for the three power supplies). in this configuration, the 4th power supply is off and can not be used. d1- d4 is not considered, but must be valid. the pok signal can be used as a global system reset. table 5-1. d1-d4 signal assignment digital interface signal supply enable d1 enables boost1 d2 enables buck2 d3 enables ldo3 d4 enables ldo4 d1 d2 d3 d4 itb/rdy pok 0 or 1 power ok open or 1
14 6266a?pmaac?08-sep-08 at73c224 figure 5-4. configurable static mode the state of each channel is determined by the internal state machine during the start-up sequence. pok is looped back onto itb/rdy. w hen this signal changes from 0 to 1 (i.e., the start-up is completed), the control of each supply channel is passed on to d1-d4. this allows changing the output values defined by the state machine. this mode can be used when the 4th channel is needed. figure 5-5. gpio (c controlled) when the system is powered, the microcontroller is not necessarily well configured and may be unable to drive d1-d4 correctly. since itb/rdy is not actively controlled, its state is an unknown logic level. if itb/rdy is in hi -z, the weak internal pullup pulls the level to 1. the power channels are controlled by the internal state machine. a fter some initialization time, the microcontroller configures its gpios to drive d1-d4 as wished. at the end of the software configuration, the microcontroller changes the level of itb/rdy to 0 in order to get control on the four power chan- nels through d1-d4. 5.3.2 dynamic mode for the devices of the AT73C224-X family that work in dynamic mode, supply management can be performed by the spi or twi digital interface. selection between the two digital interfaces is done through d4 pin when the AT73C224-X is enabled. pin d4 is a digital input pin that features a controllable pull-up resistor with active low control signal. when the AT73C224-X starts, the pullup is disabled until a push button event is detected. the state machine enables the pull-up resistor on d4, waits for a time and then checks back on the value on the pad. if d4 is high (i.e., the level externally applied on d4 is hz or logic 1), spi interface is selected. d4 will become scs. if d4 is low (i.e., d4 is externally ground ed), twi interface is selected. d4 is not used. after signal dynamic has been determined the state machine disables the pull-up resistor to save power and the d4 pin can be normally used (if spi has been selected). d1 d2 d3 d4 itb/rdy pok 01 power ok d1 d2 d3 d4 itb/rdy pok i/o i/o i/o i/o i/o c rst or nmi
15 6266a?pmaac?08-sep-08 at73c224 the selection between spi versus twi is performed once, each time the start-up sequence is executed. a timing diagram of the interface selection is shown in figure 5-6. care must be taken to leave enough time between the activation of the pullup and the moment when d4 is sampled back. this time is necessary to load the capacitance of the net layout where d4 is connected through the pull-up resistor (100 k ? typ.). this time is in the order of magnitude of 1 s (10 pf * 100 k ? ), i.e. only a few cycles of the 900 khz oscillator are needed. figure 5-6. dynamic mode interface selection note: 1. on d4, i = input pad with controllable pull-up resistor. 5.3.2.1 spi operation when spi mode is selected, the control interfac e to the AT73C224-X chip is a 4-wire interface modeled after commonly available microcontroller and serial-peripheral devices. the interface consists of a serial clock (sck), chip select (scs ), serial data input (sdi) and serial data output (sdo). data is transferred one byte at a time wi th each register access consisting of a pair of byte transfers. figure 5-7 below illustrates read and wr ite operations in spi mode. d4 d4 pull-up control signal hz spi selected, d4 => scs d4 d4 pull-up control signal twi selected dynamic dynamic scs = serial chip select table 5-2. digital interf ace selection digital signal interface pad spi selection twi selection signal direction signal direction d1 i sck in twck in d2 bidir sdo out twd i/o d3 i sdi in select the 7-bit fixed address in d4 (1) i scs in grounded -
16 6266a?pmaac?08-sep-08 at73c224 figure 5-7. spi read and write operations the first byte of a pair is the command/ address byte. the most significant bit of this byte indi- cates register read when 1 and register write when 0. the remaining seven bits of the command/address byte indicate the address of the register to be accessed. the second byte of the pair is the data byte . during a read operation, the sdo becomes active and the 8-bit contents of the register are driven out msb first. the sdo will be in high imped- ance on either the falling edge of sck following the lsb or the ri sing edge of scs, whichever occurs first. sdi is a don't care during the data portion of read operations. during write operations, data is driven into the AT73C224-X via the sdi pin, msb first. the sdo pin will remain in high imped- ance during write operat ions. data always transitions with th e falling edge of the clock and is latched on the rising edge. the clock should re turn to a logic high when no transfer is in progress. continuous clocking : in normal operation, the sck should not transition out of byte transfer periods. however, in test mode, the sck is used as the main clock. this implies that all data transfers must be controlled by the assertion of the scs pin. 3-wire operation : sdi and sdo can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data-byte transfer of a read operation. sck vs internal clock rates : it is very likely that the bit rate commanded by sck will be much higher than the internal clock (900 khz/64) used to read and write the registers. this implies that a minimal delay between byte transfers must be imposed to allow some time to decode the address and actually access the physical register. it is not acceptable to sample sck with the internal clock. 0a6a5a4a3a2a1a0 d7d6d5d4d3d2d1 sck scs sdi sdo d0 spi write sck scs sdi sdo 1 a6 a5a4 a3a2a1 a0 hz spi read d7 d6 d5 d4 d3 d2 d1 d0 hz
17 6266a?pmaac?08-sep-08 at73c224 5.3.2.2 twi operation the twi interface allows a microcontroller to proceed to read or write accesses to the internal registers of the AT73C224-X. unlike the spi, the twi operation is based on a standard which defines a data-link layer and an addressing scheme. the twi implementation used in the AT73C224-X conforms to this standard, with the following restrictions: slave only bit rate: 400 kbps max 7-bit fixed address: the default value is 1001001 (d3 is high). but the external d3 bit can modify it. when d3 is low, the 7-bit fixed address is 1001000 . twck is an input pin for the clock twd is a bidirectional pin driving (open drain with external resistor connected to v ddio ) or receiving the serial data. the data put on twd line must be 8 bits long. data is transferred msb first. each byte must be followed by an acknowledgement. each transfer begins with a start condition and terminates with a stop condition. a high-to-low transition on twd while twck is high defines a start condition. a low-to-high transition on twd while twck is high defines a stop condition. figure 5-8. twi start/stop condition figure 5-9. twi protocol after the host initiates a start condition, it sends the 7-bit slave address, as defined above, to notify the slave device. a read/write bit follows (read = 1, write = 0). the device acknowledges each received byte. the first byte sent after device address and r/w bit is the address of the device register the host wants to read or write. for a write operation, the data follows the internal address. for a read operation, a repeated start condition needs to be generated followed by a read on the device. write and read operations are shown in figure 5-8 and figure 5-9 . start stop twd twck start twd twck stop address data ack ack data ack r/w
18 6266a?pmaac?08-sep-08 at73c224 the twi abbreviations are defined below. figure 5-10. write operation figure 5-11. read operation 5.3.3 interrupt controller in dynamic mode, the itb/rdy pin is an output and operates as an interrupt to an external microcontroller. the output logic is active low (a 0 level means interrupt). several sources can potentially trigger an interrupt: the rtc, when a real-time alarm event occurs (see section 7.8 ?real-time clock (rtc)? for more details) the push-button, when its state changes the power monitor, when it detects a failure or main battery lower than 2.7v the boost, when it detects a failure the buck, when it detects a failure each of these sources can be individually masked to disable the corresponding interrupt. all the interrupt logic can also be globally disabled when the microcontroller needs to enter an uninter- ruptible state. the interrupt enable/disable logic is controlled through two independent registers. refer to section 6. ?register tables? for detailed register and bit assignment. irq_en is used to enable the interrupts, while irq_dis is used to disable the interrupts. this strategy allows the controlling software to handle the interrupt mask completely independently for each interrupt source while avoiding read-modify-write operations. the register irq_msk can be read to know the current interrupt mask. the sequence shown below in table 5-3 shows an example of interrupt masking/unmasking. s = start a = acknowledge p = stop n = not acknowledge w = write addr = device address r = read iaddr = internal address twd s addr a w iaddr a ap data twd s addr a w iaddr a s addr r a n p data table 5-3. interrupt masking/unmasking action what it does contents of irq_msk reset disables all interrupts individually and globally. 00000000 write 00000101 in irq_en enables the rtc interrupt and the power failure interrupt individually. the interrupts are still globally masked, no interrupt can be triggered yet. 00000101 write 00000000 in irq_en nothing happens, only bits set at one have an effect. 00000101 write 10000000 in irq_en enables the interrupts globally. the itb pin will toggle to 0 if either the rtc or the power monitor requests an interrupt. 10000101 write 00000001 in irq_dis disables the rtc interrupt. the power failure interrupt remains active. 10000100
19 6266a?pmaac?08-sep-08 at73c224 once the interrupt request is active on the itb/rdy pin, the microcontroller has to handle it. to determine the reason for being interrupted, it reads the interrupt status register irq_sta (this action resets itb/rdy). in this register, each potential interrupt source has a bit which indicates if it is responsible for triggering the request. once the source is identified, the microcontroller performs the handling routine in an application- dependant manner. it then needs to acknowledge the interrupt source to avoid being interrupted again for the same reason.
20 6266a?pmaac?08-sep-08 at73c224 6. register tables default values appear beneath the bit fields in the register description tables that follow. 6.1 system registers 6.1.1 7-bit fixed address for twi register name: twiaddr access type: read-only address: 0x01 addr: reads the twi address currently in use. this field can be used to check the connectivity of the twi, or to identify the AT73C224-X device. when alt bit is 0, addr contains the al ternate address (0x48). when alt is 1, addr contains the default address (0x49). alt: indicates if the twi address is the default or the alternate. 0: the default address is selected. 1: the alternate address is selected. the reset value depends on the configuration of the fuses. when the fuses are blank, the re set value is 0 (manufacturing default). 6.1.2 button status register register name: bt_sr access type: read-only address: 0x02 low: 0: the button input has not been seen low. 1: the button input has been seen low. high: 0: the button input has not been seen high. 1: the button input has been seen high. 76543210 alt addr 11001001 76543210 ??????highlow 00
21 6266a?pmaac?08-sep-08 at73c224 6.1.3 button status clear command register register name: bt_sccr access type: write-only address: 0x03 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. low: 0: no effect. 1: clears low in bt_sr. high: 0: no effect. 1: clears high in bt_sr. 6.1.4 button interrupt enable register register name: bt_ier access type: write-only address: 0x04 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. low: 0: no effect. 1: the button low in terrupt is enabled. high: 0: no effect. 1: the button high interrupt is enabled. 76543210 ??????highlow 00 76543210 ??????highlow 00
22 6266a?pmaac?08-sep-08 at73c224 6.1.5 button interrupt disable register register name: bt_idr access type: write-only address: 0x05 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. low: 0: no effect. 1: the button low interrupt is disabled. high: 0: no effect. 1: the button high interrupt is disabled. 6.1.6 button interrupt mask register register name: bt_imr access type: read-only address: 0x06 low: 0: the button low interrupt is disabled. 1: the button low in terrupt is enabled. high: 0: the button low interrupt is disabled. 1: the button low in terrupt is enabled. 6.1.7 software shutdown command register register name: shutdn access type: write-only address: 0x07 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. 0: no effect. 1: shutdown the whole chip. 76543210 ??????highlow 00 76543210 ??????highlow 00 76543210 ???????low 0
23 6266a?pmaac?08-sep-08 at73c224 6.2 pmu registers 6.2.1 boost command register register name: bst_clr access type: read/write address: 0x10 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. en: writing en to 1 starts the boost/sepic converter. writing en to 0 stops the boost/sepic converter. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 76543210 ???????en(*)
24 6266a?pmaac?08-sep-08 at73c224 6.2.2 boost configuration register register name: bst_cfg access type: read/write address: 0x11 ishort: selects the overcurrent threshold. when the external sens e resistor is 50 mohms, the lookup table below applies. at the startup, it is recommended to put 1 amp over current threshold in order not to generate a reset of the product. 76543210 ???? ishort 1011 ishort threshold (amps) 0000b 0.5 0001b 1.0 0010b 1.5 0011b 2.0 0100b 2.5 0101b 3.0 0110b 3.5 0111b 4.0 1000b 4.5 1001b 5.0 1010b 5.5 1011b 6.0 1100b 6.5 1101b 7.0
25 6266a?pmaac?08-sep-08 at73c224 6.2.3 boost voltage register register name: bst_volt access type: read/write address: 0x12 vout: selects the output voltage of the regulator following the table below. vout should always be higher than vdd1 in boos t configuration (application schematic 1). it can be programme d lower in sepic configuration (application schematic 2). (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). the chosen value should always be higher than the supply of the cell (vdd1). 76543210 ?? vout (*) v out [5:0] v out [v] v out [5:0] v out [v] 000000 not permitted 010101 3.3 000001 not permitted 010110 3.4 000010 not permitted 010111 3.5 000011 not permitted 011000 3.6 000100 not permitted 011001 3.7 000101 not permitted 011010 3.8 000110 not permitted 011011 3.9 000111 not permitted 011100 4.0 001000 not permitted 011101 4.1 001001 not permitted 011110 4.2 001010 not permitted 011111 4.3 001011 not permitted 100000 4.4 001100 not permitted 100001 4.5 001101 not permitted 100010 4.6 001110 not permitted 100011 4.7 001111 not permitted 100100 4.8 010000 not permitted 100101 4.9 010001 not permitted 100110 5.0 010010 not permitted 100111 5.1 010011 not permitted 101000 5.2 010100 3.2 ?
26 6266a?pmaac?08-sep-08 at73c224 6.2.4 buck2 control register register name: bck_ctrol access type: read/write address: 0x13 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. en: writing en to 1 starts the buck converter. writing en to 0 stops the buck converter. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). byp: writing byp to 1 puts the buck2 output voltage to vdd2. writing byp to 0 configures the buck2 in normal operation (default). 76543210 ??????bypen(*)
27 6266a?pmaac?08-sep-08 at73c224 6.2.5 buck2 configuration register register name: bck_cfg access type: read/write address: 0x14 ishort: selects the overcurrent threshold. when the external sens e resistor is 50 mohms, the lookup table below applies. mode: selects the pwm pulse skipping mode. slim: selects the power-up mode. 0: current limitation. 1: slow start. 76543210 outz slim mode ishort 11001000 ishort threshold (amps) 0000b 1.01 0001b 1.08 0010b 1.15 0011b 1.22 0100b 1.29 0101b 1.36 0110b 1.43 0111b 1.5 1000b 1.57 1001b 1.64 1010b 1.71 1011b 1.78 1100b 1.85 1101b 1.92 1110b 1.99 1111b 2.06 mode operation 00 auto 01 pwm 10 pulse skipping 11 pass-through
28 6266a?pmaac?08-sep-08 at73c224 outz: defines the state of the voltage output when the converter is off. 0: the output is forced to ground. 1: the output is left floating (hz).
29 6266a?pmaac?08-sep-08 at73c224 6.2.6 buck2 voltage register register name: bck_volt access type: read/write address: 0x15 vout: selects the output voltage of the regulator following the table below. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 76543210 ??? vout(*) v out [4:0] v out [v] v out [4:0] v out [v] 00000 0.9 10000 1.28 00001 1.0 10001 1.42 00010 1.1 10010 1.56 00011 1.2 10011 1.7 00100 1.3 10100 1.86 00101 1.4 10101 2.00 00110 1.5 10110 2.14 00111 1.6 10111 2.29 01000 1.7 11000 2.43 01001 1.8 11001 2.57 01010 1.9 11010 2.71 01011 2.0 11011 2.86 01100 2.1 11100 3.00 01101 2.2 11101 3.14 01110 2.3 11110 3.30 01111 2.4 11111 3.42
30 6266a?pmaac?08-sep-08 at73c224 6.2.7 ldo3 control register register name: ldo3_ctrl access type: read/write address: 0x16 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. en: writing en to 1 starts the ldo3 regulator. writing en to 0 stops the ldo3 regulator. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 6.2.8 ldo3 configuration register register name: ldo3_cfg access type: read/write address: 0x17 outz: defines the state of the voltage output when the regulator is off. 0: the output is forced to ground. 1: the output is left floating (hz). this bit should be at 1 when ldo is on. mode: 0: rf mode, i max = 100 ma. 1: smoother mode, i max = 200 ma. 76543210 ???????en(*) 76543210 ?????modeoutz? 11
31 6266a?pmaac?08-sep-08 at73c224 6.2.9 ldo3 voltage register register name: ldo3_volt access type: read/write address: 0x18 vout selects the output voltage of the regulator following the table below. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 76543210 ???? vout(*) v out [3:0] v out [v] 1000 1.3 0000 1.5 0001 1.6 0010 1.7 0011 1.8 0100 2.5 0101 2.6 0110 2.7 0111 2.8 1001 3.3 1010 4.9 others ?
32 6266a?pmaac?08-sep-08 at73c224 6.2.10 ldo4 control register register name: ldo4_ctrl access type: read/write address: 0x19 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. en: writing en to 1 starts the ldo4 regulator. writing en to 0 stops the ldo4 regulator. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 6.2.11 ldo4 configuration register register name: ldo4_cfg access type: read/write address: 0x1a outz: defines the state of the voltage output when the regulator is off. 0: the output is forced to ground. 1: the output is left floating (hz). this bit should be at 1 when ldo is on. mode: 0: rf mode, i max = 100 ma. 1: smoother mode, i max = 200 ma. 76543210 ???????en(*) 76543210 ?????modeoutz? 11
33 6266a?pmaac?08-sep-08 at73c224 6.2.12 ldo4 voltage register register name: ldo4_volt access type: read/write address: 0x1b vout selects the output voltage of the regulator following the table below. (*): default value depends on the chosen AT73C224-X device (see section 5.2 ). 76543210 ???? vout(*) 0111 v out [3:0] v out [v] 1000 1.3 0000 1.5 0001 1.6 0010 1.7 0011 1.8 0100 2.5 0101 2.6 0110 2.7 0111 2.8 1001 3.3 1010 4.9 others ?
34 6266a?pmaac?08-sep-08 at73c224 6.2.13 pmu status register register name: pmu_sr access type: read-only address: 0x1c short1: 0: no overcurrent condition. 1: an overcurrent condition has been detected on the boost/sepic1 converter. pg1: 0: no power good condition on boost/sepic1. 1: the power good condition has been met on boost/sepic1. pf1: 0: no power failure co ndition on boost/sepic1. 1: the power failure condition has been met on boost/sepic1. pg2: 0: no power good condition on buck2. 1: the power good condition has been met on buck2. pf2: 0: no power failure condition on buck2. 1: the power failure condition has been met on buck2. 76543210 ? ? pf2 pg2 ? pf1 pg1 short1 00000000
35 6266a?pmaac?08-sep-08 at73c224 6.2.14 pmu status clear command register register name: pmu_sccr access type: write-only address: 0x1d a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. short1: 0: no effect. 1: clears short1 in the pmu_sr. pg1: 0: no power good condition on boost/sepic1. 1: clears pg1 in the pmu_sr. pf1: 0: no effect. 1: clears pf1 in the pmu_sr. pg2: 0: no effect. 1: clears pg2 in the pmu_sr. pf2: 0: no effect. 1: clears pf2 in the pmu_sr. 76543210 ? ? pf2 pg2 ? pf1 pg1 short1 ?? ???
36 6266a?pmaac?08-sep-08 at73c224 6.2.15 pmu interrupt enable register register name: pmu_ier access type: write-only address: 0x1e a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. short1: 0: no effect. 1: the overcurrent detection interrupt on boost/sepic1 is enabled. pg1: 0: no effect. 1: the power good interrupt of boost/ sepic1 is enabled. pf1: 0: no effect. 1: the power fail interrupt of boost/sepic1 is enabled. pg2: 0: no effect. 1: the power good interrupt of buck2 is enabled. pf2: 0: no effect. 1: the power fail interrupt of buck2 is enabled. 76543210 ? ? pf2 pg2 ? pf1 pg1 short1 ??00?000
37 6266a?pmaac?08-sep-08 at73c224 6.2.16 pmu interrupt disable register register name: pmu_idr access type: write-only address: 0x1f a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. short1: 0: no effect. 1: the overcurrent detection interrupt on boost/sepic1 is disabled. pg1: 0: no effect. 1: the power good interrupt of boost/ sepic1 is disabled. pf1: 0: no effect. 1: the power fail interrupt of boost/sepic1 is disabled. pg2: 0: no effect. 1: the power good interrupt of buck2 is disabled. pf2: 0: no effect. 1: the power fail interrupt of buck2 is disabled. 76543210 ? ? pf2 pg2 ? pf1 pg1 short1 ?? ???
38 6266a?pmaac?08-sep-08 at73c224 6.2.17 pmu interrupt mask register register name: pmu_imr access type: read-only address: 0x20 a minimum of 3 clock cycles of 15 khz clock must be waited after any read operation before doing a new register access. short1: 0: the overcurrent detection interrupt on boost/sepic1 is disabled. 1: the overcurrent detection interrupt on boost/sepic1 is enabled. pg1: 0: the power good interrupt of boost/ sepic1 is disabled. 1: the power good interrupt of boost/ sepic1 is enabled. pf1: 0: the power fail interrupt of boost/sepic1 is disabled. 1: the power fail interrupt of boost/sepic1 is enabled. pg2: 0: the power good interrupt of buck2 is disabled. 1: the power good interrupt of buck2 is enabled. pf2: 0: the power fail interrupt of buck2 is disabled. 1: the power fail interrupt of buck2 is enabled. 76543210 ? ? pf2 pg2 ? pf1 pg1 short1 00 000
39 6266a?pmaac?08-sep-08 at73c224 6.3 interrupt registers 6.3.1 interrupt enable register register name: irq_en access type: write-only address: 0x30 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. rtc: enables the rtc interrup t when written to 1. writing 0 has no effect. pb: enables the push-button interrupt when written to 1. writing 0 has no effect. pwr: enables the power failure in terrupt when written to 1. writing 0 has no effect dc1: enables the boost/sepic1 interrupt when written to 1. writing 0 has no effect. dc2: enables the buck2 interrupt when written to 1. writing 0 has no effect. all: writing to 1 globally enables all the interrupt sources that had been previously enabled individually. the interrupt setting fo r each source is restored. writing 0 has no effect. 76543210 all ? dc2 dc1 ? pwr pb rtc ??????
40 6266a?pmaac?08-sep-08 at73c224 6.3.2 interrupt disable register register name: irq_dis access type: write-only address: 0x31 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. rtc: disables the rtc interrup t when written to 1. writing 0 has no effect. pb: disables the push-button interrupt when written to 1. writing 0 has no effect. pwr: disables the power failure in terrupt when written to 1. writing 0 has no effect dc1: disables the boost/sepic1 interrupt when written to 1. writing 0 has no effect. dc2: disables the buck2 interr upt when written to 1. writing 0 has no effect. all: writing to 1 globally disables all the interrupt sources. the individual setting of each interrupt source is saved. writing 0 has no effect. 76543210 all ? dc2 dc1 ? pwr pb rtc ??????
41 6266a?pmaac?08-sep-08 at73c224 6.3.3 interrupt mask register register name: irq_msk access type: read-only address: 0x32 this register summarizes the result of the successive interrupt enable/disable commands performed by writing into irq_en/irq_dis. rtc: 0: the rtc interr upt is masked. 1: the rtc interr upt is unmasked. pb: 0: the push-button interrupt is masked. 1: the push-button interrupt is unmasked. pwr: 0: the power failure interrupt is masked. 1: the power failure interrupt is unmasked. dc1: 0: the boost/sepic1 interrupt is masked. 1: the boost/sepic1 in terrupt is unmasked. dc2: 0: the buck2 interrupt is masked. 1: the buck2 interrupt is unmasked. all: 0: the interrupt sources are globally masked. 1: the interrupt sources are globally unmasked. 76543210 all ? dc2 dc1 ? pwr pb rtc 00000000
42 6266a?pmaac?08-sep-08 at73c224 6.3.4 interrupt status register register name: irq_sta access type: read-only address: 0x33 a minimum of 3 clock cycles of 15 khz clock must be waited after any write operation before doing a new register access. reading irq de-asserts the itb signal. rtc: 1: signals a pending interrupt request from the rtc. pb: 1: signals a pending interrupt request from the push-button. pwr: 1: signals a pending interrupt request from the power monitor. dc1: 1: signals a pending interrupt requ est from the boost/sepic1. dc2: 1: signals a pending interrupt request from the buck2. 76543210 ? ? dc2 dc1 ? pwr pb rtc 00000000
43 6266a?pmaac?08-sep-08 at73c224 6.4 rtc registers 6.4.1 rtc control register register name: rt_cr access type: read/write address: 0x40 updtim: writing 1 requests the rtc to stop the time counter so that it can be safely updated. the time counter is actually stopped only when ackupd is set in rtc_sr. writing 0 restarts the time counter. updcal: writing 1 requests the rtc to stop the calendar counter so that it can be safely updated. the calendar counter is actually stopped only when ackupd is set in rtc_sr. writing 0 restarts the calendar counter. timevsel: selects the type of event to cause timev to change in rtc_sr. calevsel: selects the type of event to cause calev to change in rtc_sr. 76543210 calevsel timevsel ? ? updcal updtim 0000 00 00 minute change 01 hour change 10 every day at midnight 11 every day at noon 00 week change every monday at time 00:00:00 01 month change every 1st of each month at time 00:00:00 10 11 year change every 1st of january at time 00:00:00
44 6266a?pmaac?08-sep-08 at73c224 6.4.2 rtc reset register register name: rt_rr access type: read/write address: 0x41 rst: rst = 0, normal operation rst=1, reset the rtc 6.4.3 rtc mode register register name: rt_mr access type: read/write address: 0x44 hrmod: 0: 24-hour mode. 1: 12-hour mode. 76543210 rst??????? 0 76543210 ???????hrmod 0
45 6266a?pmaac?08-sep-08 at73c224 the three time writing registers are only writable concomitantly and must be written in the order as shown below: 1. rt_sec 2. rt_min 3. rt_hour 6.4.4 real-time second register register name: rt_sec access type: read/write address: 0x48 sec: the range is 0-59 encoded in binary coded decimal (bcd). the lowest four bits encode the units, the higher bits encode the tens. this field must not be written unless the time counter has been stopped. 6.4.5 real-time minute register register name: rt_min access type: read/write address: 0x49 min the range is 0-59 encoded in bcd. the lowest four bits enc ode the units, the higher bits encode the tens. this field must not be written unless the time counter has been stopped. 6.4.6 real-time hour register register name: rt_hour access type: read/write address: 0x4a hour: depending on bit ampm, the range can be 1-12 or 0-23, encoded in bcd. the lowest four bits encode the units, the higher bits encode the tens. this field must not be written unless the time counter has been stopped. ampm: this bit controls/reflects the am /pm indicator in 12-hour mode. 0: am. 1: pm. 76543210 ?sec 0000000 76543210 ?min 0000000 76543210 ?ampm hour 0000000
46 6266a?pmaac?08-sep-08 at73c224 the four date writing registers are only writable concomitantly and must be written in the order as shown below: 1. rt_cent 2. rt_year 3. rt_month 4. rt_date 6.4.7 real-time century register register name: rt_cent access type: read/write address: 0x4c cent: the range is 19 - 20, encoded in bcd. the lowest four bits encode the units, the higher bits encode the tens. 6.4.8 real-time year register register name: rt_year access type: read/write address: 0x4c year: the range is 1 - 12, encoded in bcd. the lowest four bits encode the units, the higher bits encode the tens. 6.4.9 real-time month register register name: rt_month access type: read/write address: 0x4e month: the range is 1 - 12, encoded in bcd. the lowest four bits encode the units, the higher bits encode the tens. day: the range is 1-7 and represents the day of the week. the relati onship between the coding of this field and the actual day of the week, is user-defined. especially, writing to this bit has no effect on the date counter. 76543210 ? ? cent 011001 76543210 year 10011000 76543210 day month 10000001
47 6266a?pmaac?08-sep-08 at73c224 6.4.10 real-time date register register name: rt_date access type: read/write address: 0x4f date: the range is 1 - 31, encoded in bcd and represents the day of the month. the lowest four bits encode the units, the higher bits encode the tens. 76543210 day date 10011000
48 6266a?pmaac?08-sep-08 at73c224 the three time alarm writing registers are only writable concomitantly and must be written in the order as shown below: 1. rt_seca 2. rt_mina 3. rt_houra 6.4.11 real-time second alarm register register name: rt_seca access type: read/write address: 0x50 sec: this field is the alarm field corresponding to the bcd-encoded second counter. secen 0: the second-matching alarm is disabled. 1: the second-matching alarm is enabled. 6.4.12 real-time minute alarm register register name: rt_mina access type: read/write address: 0x51 min: this field is the alarm field corresponding to the bcd-encoded minute counter. minen 0: the minute-matching alarm is disabled. 1: the minute-matching alarm is enabled. 76543210 secen sec 00000000 76543210 minen min 00000000
49 6266a?pmaac?08-sep-08 at73c224 6.4.13 real-time hour alarm register register name: rt_houra access type: read/write address: 0x52 hour: this field is the alarm field corresponding to the bcd-encoded hour counter. ampm: this field is the alarm field corresponding to the bcd-encoded hour counter. houren 0: the hour-matching alarm is disabled. 1: the hour-matching alarm is enabled. 76543210 houren ampm hour 00000000
50 6266a?pmaac?08-sep-08 at73c224 the two date alarm writing registers are only writable concomitantly and must be written in the order as shown below: 1. rt_montha 2. rt_datea 6.4.14 real-time month alarm register register name: rt_montha access type: read/write address: 0x56 month: this field is the alarm field corresponding to the bcd-encoded month counter. mthen 0: the month-matching alarm is disabled. 1: the month-matching alarm is enabled. 6.4.15 real-time date alarm register register name: rt_datea access type: read/write address: 0x56 date: this field is the alarm field corresponding to the bcd-encoded day of the month counter. dateen: 0: the day of the month-matching alarm is disabled. 1: the day of the month-matching alarm is enabled. 76543210 mthen ? ? month 0 00001 76543210 dateen ? date 0 000001
51 6266a?pmaac?08-sep-08 at73c224 6.4.16 rtc status register register name: rtc_sr access type: read-only address: 0x58 ackupd: 0: time and calendar registers should not be updated. 1: time and calendar can be updated safely (clock stopped). alarm: 0: no alarm matching condition occurred. 1: an alarm matching condition occurred. sec: 0: no second event has occurred since last clear. 1: at least one second event occurred since last clear. timev: 0: no time event has occurred since last clear. 1: at least one time event occurred since last clear. the time event is selected by the timevsel field in rtc_cr and can be any of the following events: minute change, hour change, noon, midnight (day change). calev: 0: no calendar event occurred since last clear. 1: at least one calendar event occurred since last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any of the following events: week change, month change, or year change. 76543210 ? ? ? calev timev sec alarm ackupd 00000
52 6266a?pmaac?08-sep-08 at73c224 6.4.17 rtc status clear command register register name: rtc_sccr access type: write-only address: 0x5c ackclr: 0: no effect. 1: clears the ackupd bit in rtc_sr. alclr: 0: no effect. 1: clears the alarm bit rtc_sr. secclr: 0: no effect. 1: clears the sec bit rtc_sr. timclr: 0: no effect. 1: clears the timev bit rtc_sr. calcr: 0: no effect. 1: clears the calev bit rtc_sr. 76543210 ? ? ? calclr timclr secclr alrclr ackclr 00000
53 6266a?pmaac?08-sep-08 at73c224 6.4.18 rtc interrupt enable register register name: rtc_ier access type: write-only address: 0x60 acken: 0: no effect. 1: the acknowledge for update interrupt is enabled. alren: 0: no effect. 1: the alarm interrupt is enabled. secen: 0: no effect. 1: the second periodic interrupt is enabled. timen: 0: no effect. 1: the selected time event interrupt is enabled. calen: 0: no effect. 1: the selected calendar event interrupt is enabled. 76543210 ? ? ? calen timen secen alren acken 00000
54 6266a?pmaac?08-sep-08 at73c224 6.4.19 rtc interrupt disable register register name: rtc_idr access type: write-only address: 0x64 ackdis: 0: no effect. 1: the acknowledge for update interrupt is disabled. alrdis: 0: no effect. 1: the alarm interrupt is disabled. secdis: 0: no effect. 1: the second periodic interrupt is disabled. timdis: 0: no effect. 1: the selected time event interrupt is disabled. caldis: 0: no effect. 1: the selected calendar event interrupt is disabled. 76543210 ? ? ? caldis timdis secdis alrdis ackdis 00000
55 6266a?pmaac?08-sep-08 at73c224 6.4.20 rtc interrupt mask register register name: rtc_imr access type: read-only address: 0x68 ack: 0: the acknowledge for update interrupt is disabled. 1: the acknowledge for update interrupt is enabled. alr: 0: the alarm interrupt is disabled. 1: the alarm interrupt is enabled. sec: 0: the second periodic interrupt is disabled. 1: the second periodic interrupt is enabled. tim: 0: the selected time event interrupt is disabled. 1: the selected time event interrupt is enabled. cal: 0: the selected calendar event interrupt is disabled. 1: the selected calendar event interrupt is enabled. 76543210 ???caltimsecalrack 00000
56 6266a?pmaac?08-sep-08 at73c224 6.4.21 rtc valid entry register register name: rtc_ver access type: read-only address: 0x6c nvtim: 0: no invalid data has been detected in the time registers. 1: invalid data has been detected. nvcal: 0: no invalid data has been detected in the calendar registers. 1: invalid data has been detected. nvtima: 0: no invalid data has been detected in the time alarm registers. 1: invalid data has been detected. nvcala: 0: no invalid data has been detected in the calendar alarm registers. 1: invalid data has been detected. 76543210 ????nvcalanvtimanvcalnvtim
57 6266a?pmaac?08-sep-08 at73c224 7. electrical characteristics with external components as listed in table 4-1 , ta = -40c to 85c typical values are at ta = 25c (unless otherwise specified). 7.1 absolute maximum ratings 7.2 recommended o perating conditions table 7-1. absolute maximum ratings operating temperature (industrial).............-40 c to + 85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other c onditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. storage temperature..................................-55c to + 150c power supply input.................... ....................-0.3v to + 5.5v i/o input.......................................................... -0.3v to + 5.5v esd (all pins)-..................................................................2 kv table 7-2. recommended operating conditions parameter condition min max unit operating temperature -40 85 c power supply input 2.8 5.25 v
58 6266a?pmaac?08-sep-08 at73c224 7.3 digital i/os digital i/os are supplied by vddio. vddio is an input and must be externally connected. . vddio referred pins en, d1, d3, d4: cmos inputs. only vih and vil parameters are applicable. vddio referred pins pok: cmos output. only vol, voh parameters are applicable. vddio referred pin itb, d2: cmos bidir. all parameters applicable. 7.4 current consumption versus modes table 7-3. vddio referred digital i/os symbol parameter conditions min typ max unit vddio operating supply voltage 1.75 3.6 5.25 v v il input low level voltage -0.3 0.3x vddio v v ih input high level voltage 0.7x vddio vddio + 0.3 v v ol output low level voltage 0.75x vddio v v oh output high level voltage 0.25x vddio v io output current 8ma rp pull-up or pull down resistance when applicable 90 120 150 k ? table 7-4. quiescent current in dif ferent operating modes status conditions battery current typ max off no battery is present n/a n/a backup mode no main battery is present backup battery present (and charged): . running: rtc (dig + oscillator 32 khz) - supply: vbackup pin 1 a 2 a stand by main battery plugged in and higher than 2.8v backup battery present (and charged) . power supplies off (boost1, buck2, ldo3, ldo4) . running: rtc, ldo_rtc - supply: vbat_ldortc por, lpbg, vmon - supply: vdd0 pin 4a 9a 7a 17a
59 6266a?pmaac?08-sep-08 at73c224 7.5 boost1: step-up converter note: 1. before the boost is turned on, it is recommended to esta blish low current limitation (typic: 1 amp) to avoid current pea k on main supply. table 7-5. boost1 electrical characteristics symbol parameter conditions min typ max unit vdd1 operating supply voltage 2.8 3.6 5.25 v fs converter frequency 400 900 1400 khz i o load current 1a vo1 output voltage bst_volt register (@12) - step 100 mv vdd1 < vo1 3.2 5.2 v error output voltage precision iload > 100 ma -10 -10 % i sc shutdown current bst_clr register (@10); en = 0 1 a i lim current limitation bst_cfg register (@11) 0.5 7 (1) a 2.8 _3.3_1a efficiency at vdd1 = 2.8 v i o = 1 a, vdd1 = 2.8v, vo1 = 3.3v 90 % h3.6_5.2_1a efficiency at vdd1 = 3.6 v i o = 1 a, vdd1 = 3.3v, vo1 = 5.2v 85 % t start start-up time no load 200 s ? v o1_5.2v ripple voltage peak-to-peak, i o = 1 a, vo1 = 5.2v bandwidth = 20 mhz 200 mv ? v o1_5.2v static line regulation vdd1: 2.8 to 4.2v - i o = 1 a - vo1 = 5.2v 200 mv ? v o1_5.2v static load regulation vdd1: 3.6v - i o : 100 ma to 900 ma - vo1 = 5.2v 50 mv
60 6266a?pmaac?08-sep-08 at73c224 7.5.1 boost1: typical characteristics figure 7-1. efficiency boost1 - vo1 = 5v - iload (a) vdd1 = 3v vdd1 = 2.8v vdd1 = 4.2v vdd1 = 3.6v 60 65 70 75 80 85 90 95 100 0.01 0.1 1
61 6266a?pmaac?08-sep-08 at73c224 figure 7-2. load regulation boost1 - vo1 = 5v - the boost1 cell can be implemented using proper external components. (see figure 4-3 ?application schematic 3: boost in sepic configuration (buck/boost)? .) iload (a) vdd1 = 3v vdd1 = 2.8v vdd1 = 4.2v vdd1 = 3.6v 5.02 5.04 5.06 5.08 5.1 5.12 5.14 5.16 5.18 5.2 5.22 5.24 5.26 5.28 5.3 5.32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
62 6266a?pmaac?08-sep-08 at73c224 7.6 buck2: step-down converter note: 1. for device commanded in dynamic mode only. for devices commanded in static mode, the minimum voltage is 1.8v. the buck2 is a pulse width mo dulator (pwm) / pulse-skippi ng (psk) synchr onous regulator that can be used to provide an accurate 0.9v to 3.4v programmable output voltage at 500 ma of maximum load current. integrated current sensing is used to sense the dc/dc converter load current used for the over- current circuit protection and for the pwm / psk mode selector. by default, the buck2 is in automatic mode: according to the load current value, the regulator is either in pulse-skipping mode (light load) or in pwm mode (high load). in dynamic mode, the user can select pwm or psk mode, using the bits 4 and 5 of the bck_cfg register (see sec- tion 6 register tables). note that the automatic mode should not be used for output voltages below 1.8v. table 7-6. buck2 electrical characteristics symbol parameter conditions min typ max unit vdd2 operating supply voltage 2.8 3.6 5.25 v fs converter frequency pwm mode 400 900 1400 khz i load load current 0.5 a vo2 output voltage bck_volt register (@15) - step 100mv vdd2 > (vo2 + 0.2v) 0.9 (1) 3.4 v error output voltage precision -10 10 % i sc shutdown current bck_ctrol register (@13), en = 0 1 6 a i stb stand-by current bck_ctrol register (@ 13), en = 1, clock not present 20 50 a i max short circuit current bck_cfg register (@14) 1 2 a i pwm-psk pwm ? pulse skipping current threshold automatic mode- vdd2 = 3.6v- vo2 = 1.8v 70 ma ? v ripple voltage pwm mode 10 mv t r rise time bandgap already started, slow-start power up selected 1 ms ? v dc static line regulation i load = 500 ma, vdd2 from 2.8v to 5v pwm mode 80 mv ? v dc static load regulation 1 ma 63 6266a?pmaac?08-sep-08 at73c224 7.6.1 buck2: typical characteristics figure 7-3. efficiency manual/automatic modes efficiency vo2 = 1.8v - manual mode: psk/pwm efficiency vo2 = 3.3v - manual mode: psk/pwm efficiency vo2 = 1.2v - manual mode: psk/pwm efficiency vo2 = 0.9v - manual mode: psk/pwm efficiency (%) iload (a) efficiency (%) efficiency (%) efficiency (%) iload (a) iload (a) iload (a) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v vdd2 = 5v vdd2 = 4.2v vdd2 = 4.2v vdd2 = 5v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 efficiency vo2 = 3.3v - automatic mode iload (a) efficiency (%) vdd2 = 4.2v vdd2 = 5v 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 efficiency vo2 = 1.8v - automatic mode iload (a) efficiency (%) vdd2 = 3.6v vdd2 = 2.8v vdd2 = 4.2v vdd2 = 5v 45 50 55 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1 pwm psk pwm psk pwm psk pwm psk
64 6266a?pmaac?08-sep-08 at73c224 7.6.2 buck2: load re gulation of vo2 figure 7-4. load regulation 0.85 0.86 0.87 0.88 0.89 0.9 0.91 0.92 0.93 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.15 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1.23 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.72 1.74 1.76 1.78 1.8 1.82 1.84 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 load regulation: vo2 = 0.9v (pwm mode) load regulation: vo2 = 1.2v (pwm mode) load regulation: vo2 = 1.8v (pwm mode) load regulation: vo2 = 3.3v (pwm mode) i load (a) i load (a) i load (a) i load (a) vo2 (v) vo2 (v) vo2 (v) vo2 (v) vdd2 = 5v vdd2 = 4.2v vdd2 = 3.6v vdd2 = 2.8v vdd2 = 2.8v vdd2 = 3.6v vdd2 = 4.2v vdd2 = 5.5v vdd2 = 2.8v vdd2 = 3.6v vdd2 = 4.2v vdd2 = 5.5v vdd2 = 5.5v vdd2 = 4.2v
65 6266a?pmaac?08-sep-08 at73c224 7.7 ldo3 & ldo4 ldo3 and ldo4 are low-drop-out voltage regulators that can provide a 1.3v, 1.5v to 1.8v (step 100 mv), 2.5v to 2.8v (100 mv step) or 3.3v output voltage. two kinds of applications are defined: ?rf? mode (high psrr and low noise) with 100 ma max- imum load and ?smoother? mode with 200 ma maximum load. by default, the ldos are configured in rf m ode. if the load is higher than 100 ma, the user should pass into smoother mode (see the register tables in section 6.2.8 ?ldo3 configuration register? and section 6.2.11 ?ldo4 configuration register? ). an external 2.2 f ceramic capacitor is needed for the st ability of each ldo. table 7-7. ldo3 and ldo4 electrical characteristics symbol parameter conditions min typ max unit vdd3&4 operating supply voltage 2.8 3.6 5.25 v i load_s smoother load current in smoother mode 0 200 ma i load_rf rf load current in rf mode 0 100 ma vo3, vo4 output voltage selection in ldo3_volt @ 18 and ldo4_volt @ 1b vdd3 > vo3 + 200mv vdd4 > vo4 + 200mv 1.3 3.3 v ? v o accuracy i load =10ma -8 8 % i sc shutdown current gnd output (ldo3_cfg@17 and ldo4_cfg@1a) 1a i qq quiescent current no load 20 a t r rise time 100 s ? v dc line regulation static 2.8v < vdd3 < 5.25v, full load 10 mv ? v dc load regulation static 10 ma 66 6266a?pmaac?08-sep-08 at73c224 7.7.1 ldo3 and ldo4: typical characteristics figure 7-5. ldo load regulation shown below is vo3 ripple (same as vo4) in response to a load current pulse from 10 ma to 200 ma. channel 2: vo3 = 1.8v and vo3 = 3.3v (50mv/div) channel 1: iload = 10 ma - 200 ma (100 ma/div) load regulation vo3 = 3.3v iload (a) vo3 (v) iload (a) load regulation vo3 = 1.8v vdd3 = 5v vdd3 = 4.2v vdd3 = 3.6v vdd3 = 3v vdd3 = 2.8v vdd3 = 5v vdd3 = 4.2v vdd3 = 3.6v 3.264 3.265 3.266 3.267 3.268 3.269 3.27 3.271 3.272 3.273 3.274 3.275 3.276 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3 1.761 1.762 1.763 1.764 1.765 1.766 1.767 1.768 1.769 1.77 1.771 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3 vo3 (v)
67 6266a?pmaac?08-sep-08 at73c224 7.8 real-time clock (rtc) the real-time clock architecture is shown in figure 7-6 and is comprised of the following blocks: 2.6v ldo_rtc voltage regulator with backup switch, rtc os cillator and rtc block. 7.8.1 block diagram figure 7-6. rtc block diagram the ldo_rtc is used to charge the backup battery at 2.6v. when the main battery is plugged in, the ldo is enabled and the backup switch is closed, thus charging the battery. if the vbackup initial value is lower than the minimum backup voltage admissible (1.8v typical), an active low reset is generated on reset signal. the c11 capacitor is used for ldo compensation while the r2 resistor limits the charge current for the backup battery. the rtc oscillator is suited to work with a 32.768 khz crys tal oscillator and generates the 32.768 khz clock for the rtc. the rtc block provides seconds, minutes, hours, days, date, month, and year information. rtc time data is stored into a register that can be accessed via the AT73C224-X device serial interface. ldo rtc 2.6v rtc osc rtc recharchable backup battery 2.5v (nbl type) rtc clock x1 32.768 khz crystal vbackup xin xout vdd0 < 2.8v switch open ldo_rtc off r2 c11 d0 to d4 serial interface vbat_ldortc AT73C224-X AT73C224-X vdd0 vmon
68 6266a?pmaac?08-sep-08 at73c224 7.8.2 ldo rtc the ldo_backup is a low drop out voltage regulator that is used to charge a 2.5v rtc rechargeable backup battery (type nbl621). the max load current is 2 ma. an external 1 f ceramic capacitor (c11) is needed for compensation. 7.8.3 rtc oscillator the rtc oscillator is a low-frequency, 2-pad, pierce-type xtal oscillator, optimized for 32.768 khz crystal. for operation with 6 pf load capacitance crystals, no external components are needed on ?xin? and ?xout?. it may be necessary to add external capacitors on ?xin? and ?xout? to ground in special cases, for example, to exactly set the frequency or for crystals with a load capacitance superior to 6 pf. the ?clock? output is low during standby. ?xin? and ?xout? must not be used to drive other circuitry. table 7-8. ldo rtc electrical characteristics symbol parameter conditions min typ max unit v bat_ldortc operating supply voltage 2.8 5.25 v v backup output voltage vbat_ldortc present 2.55 2.6 2.65 v i out load current dc load current 2 ma i qq battery quiescent current en = 1 3 5 a i bkqq backup battery quiescent current en = 0 200 300 na i sc shutdown current 1a t s start-up time 1ms v th reset threshold reset is active low 1.8 v table 7-9. rtc oscillator electrical characteristics symbol parameter conditions min typ max unit v backup supply voltage 1.75 2.65 f ck operating frequency 32.768 khz duty duty cycle 40 50 60 % ton startup time 900 ms v sin level sinus wave on xin r s = 50 k ? 160 260 360 mvpp d rv drive level r s = 50 k ? 0.1 w i current dissipation off 5 na on 0.8 2 a a cc accuracy t = 25 c 3 mn/month r s equivalent series resistan ce crystal @ 32.768khz 50 k ? c mt motional capacitance crystal @ 32.768khz 1 3 ff c shunt shunt capacitance crystal @ 32.768khz 0.6 2 pf c load load capacitance crystal @ 32.768khz 6 12.5 pf
69 6266a?pmaac?08-sep-08 at73c224 7.9 vint one external capacitor (47 0nf) is necessary on vint pin for functionality of the internal ldo supply. this voltage should not be used by the user.
70 6266a?pmaac?08-sep-08 at73c224 8. package drawing figure 8-1. qfn 32-lead package drawing (a ll dimensions in millimeters) r-qfn032_h
71 6266a?pmaac?08-sep-08 at73c224 9. revision history doc. rev. comments change request ref. 6266a first issue.
72 6266a?pmaac?08-sep-08 at73c224
i 6266a?pmaac?08-sep-08 at73c224 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 1 2 block diagram ............ ................ ................. ................ ................. ............ 3 3 pinout .............. ................. ................ ................. .............. .............. ............ 4 4 application examples .............. ................ ................. ................ ............... 5 5 detailed description ........... .............. ............... .............. .............. ............ 9 5.1 core ...................................................................................................................9 5.2 automatic start-up sequences and shut-down ...............................................10 5.3 digital control and protocol .............................................................................13 6 register tables ............... ................ ................. .............. .............. .......... 20 6.1 system registers ............................................................................................20 6.2 pmu registers ................................................................................................23 6.3 interrupt registers ...........................................................................................39 6.4 rtc registers .................................................................................................43 7 electrical characteristics ... .............. ............... .............. .............. .......... 57 7.1 absolute maximum ratings .............................................................................57 7.2 recommended operating conditions .............................................................57 7.3 digital i/os .......................................................................................................58 7.4 current consumption versus modes ..............................................................58 7.5 boost1: step-up converter ...........................................................................59 7.6 buck2: step-down converter .........................................................................62 7.7 ldo3 & ldo4 .................................................................................................65 7.8 real-time clock (rtc) ....................................................................................67 7.9 vint ................................................................................................................69 8 package drawing ......... ................. ................ ................. .............. .......... 70 9 revision history ....... ................ ................ ................. ................ ............. 71 table of contents.......... ................. ................ ................. ................ ........... i
ii 6266a?pmaac?08-sep-08 at73c224
6266a?pmaac?08-sep-08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com www.atmel.com/powermanagement technical support pmaac@atmel.com atmel techincal support sales contacts www.atmel.com/contacts/ literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site , atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequentia l, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of pr ofits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comple teness of the contents of this document and reserves the rig ht to make changes to specifica- tions and product descriptions at any time without notice. atmel does not make any commitment to update the information contain ed herein. unless specifically pro- vided otherwise, atmel products are not suitable for, and shall not be used in, automotive applic ations. atmel?s products are n ot intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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